may, 2018

17may11:00 am4:30 pmIntel Workshop

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Event Details

11am-Noon: Getting Hired into Tech, An Insiders View
Tips on resume writing, career fairs, and interviewing for those seeking internships and full time positions at tech companies.

Noon-12:30pm: Pizza Lunch from Woodstocks

12:30pm-4:30pm: Static Timing Analysis FPGA Workshop
This workshop consists of a two hour lecture/exercise session followed by a two hour lab training the fundamentals of timing analysis for digital electronics. The student will learn the foundation of timing constraints and how to calculate timing “slack” through a number of paper and pencil exercises to understand how timing margin is calculated. The second portion of this workshop will focus on Intel’s Quartus Timing Analysis tools to give the student hands on knowledge of writing timing constraints, analyzing timing slack, and working on corrective methods to improve timing margin of digital designs implemented in FPGAs.

Click here to sign up

Time

(Thursday) 11:00 am - 4:30 pm

Location

EE Lobby

Organizer

Nathan Wang[email protected]

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